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1 80v, 500ma, 3-phase mosfet driver hip4086, HIP4086A the hip4086 and HIP4086A (referred to as the hip4086/a) are three phase n-channel mosfet drivers. both parts are specifically targeted for pwm motor control. these drivers have flexible input protocol for driving every possible switch combination. the user can even override the shoot-through protection for switched reluctance applications. the hip4086/a have a wide range of programmable dead times (0.5s to 4.5s) which makes them very suitable for the low frequencies (up to 100khz) typically used for motor drives. the only difference between the hip4086 and the HIP4086A is that the HIP4086A has the built- in charge pumps disabled. this is useful in applications that require very quiet emi performance (the charge pumps operate at 10mhz). the advantage of the hip4086 is that the built-in charge pumps allow indefinitely long on times for the high-side drivers. to insure that the high-side driver boot capacitors are fully charged prior to turning on, a programmable bootstrap refresh pulse is activated when vdd is first applied. when active, the refresh pulse turns on all three of the low-side bridge fets while holding off the three high-side bridge fets to charge the high-side boot capacitors. after the refresh pulse clears, normal operation begins. another useful feature of the hip4086/a is the programmable undervoltage set point. the set po int range varies from 6.6v to 8.5v. features ? independently drives 6 n-channel mosfets in three phase bridge configuration ? bootstrap supply max voltage up to 95vdc with bias supply from 7v to 15v ? 1.25a peak turn-off current ? user programmable dead time (0.5s to 4.5s) ? bootstrap and optional charge pump maintain the high-side driver bias voltage. ? programmable bootstrap refresh time ? drives 1000pf load with typica l rise time of 20ns and fall time of 10ns ? programmable undervoltage set point applications ? brushless motors (bldc) ?3-phase ac motors ? switched reluctance motor drives ?battery powered vehicles ?battery powered tools related literature ? an9642 ?hip4086 3-phase bridge driver configurations and applications? figure 1. typical application figure 2. charge pump output current controller aho clo blo alo cho bho cli bli ali chi bhi ahi chs ahs bhs chb ahb bhb vdd rdel vdd speed brake battery 24v...48v hip4086/a vss -60 -40 -20 0 20 40 60 80 100 120 140 160 200 150 100 50 0 junction temperature (c) output current (a) v xhb - v xhs = 10v february 1, 2013 fn4220.9 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2011, 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
hip4086, HIP4086A 2 fn4220.9 february 1, 2013 block diagram (for clarity, only one phase is shown) rdel 7 xli 4 rfsh 9 uvlo 8 vdd 20 dis 10 xhi 5 2s delay refresh pulse undervoltage detector 10ns delay adjustable turn-on delay level shifter charge pump * xho 17 xhb 16 xhs 18 xlo 21 vss 6 vdd 100mv vdd *the charge pump is permanently disabled in the HIP4086A. common with all phases common with all phases common with all phases common with all phases en if the voltage on rdel is less than 100mv, the turn-on delay timers are disabled and the high and low-side drivers can be turned on simultaneously . if undervoltage is active or if dis is asserted, the high and low-side drivers are turned off. adjustable turn-on delay delay disable drive enable truth table input output ali, bli, cli ahi , bhi , chi uv dis rdel alo, blo, clo aho, bho, cho xxx1x00 xx1xx00 1 x 0 0 >100mv 1 0 0000x01 0100x00 1 0 0 0 <100mv 1 1 note: x signifies that input can be either a ?1? or ?0?.
hip4086, HIP4086A 3 fn4220.9 february 1, 2013 pin configuration hip4086, HIP4086A (pdip, soic) top view 1 bhb 2 bhi 3 bli 4 ali 5 ahi 6 vss 7 rdel 8 uvlo 9 rfsh 10 dis 11 cli 12 chi 24 bho 23 bhs 22 blo 21 alo 20 vdd 19 clo 18 ahs 17 ahc 16 ahb 15 chs 14 cho 13 chb pin descriptions pin number symbol description 16 1 13 ahb bhb chb (xhb) high-side bias connections. one external boot strap diode and one capacitor are required for each. connect cathode of bootstrap diode and posi tive side of bootstrap capacitor to each xhb pin. 15 23 15 ahs bhs chs (xhs) high-side source connections. connect the sour ces of the high-side power mosfets to these pins. the negative side of the bootstrap ca pacitors are also connected to these pins. 5 2 12 ahi bhi chi (xhi ) high-side logic level inputs. logic at these thre e pins controls the three high side output drivers, aho (pin 17), bho (pin 24) and cho (pin 14). when xhi is low, xho is high. when xhi is high, xho is low. unless the dead time is disa bled by connecting rdel (pin 7) to ground, the low side input of each phase will override the corresponding high side input on that phase - see ?truth table? on page 2. if rdel is tied to ground, dead time is disabled and the outputs follow the inputs with no shoot-thru protection. di s (pin 10) also overrides the high side inputs. xhi can be driven by signal levels of 0v to 15v (no greater than v dd ). 4 3 11 ali bli cli (xli) low-side logic level inputs. logic at these three pins controls the three low-side output drivers alo (pin 21), blo (pin 22) and clo (pin 19). if the upper inputs are grounded then the lower inputs control both xlo and xho drivers, wi th the dead time set by the resistor at rdel (pin 7). dis (pin 10) high level input overrides xl i, forcing all outputs low. xli can be driven by signal levels of 0v to 15v (no greater than v dd ). 6v ss ground. connect the sources of the low-side power mosfets to this pin. 7 rdel delay time set point. connect a resistor from this pin to v dd to set timing current that defines the dead time between drivers - see figure 17. al l drivers turn-off with minimal delay, rdel resistor prevents shoot-through by delaying the turn-on of all drivers. when rdel is tied to v ss , both upper and lowers can be commanded on simultaneously. while not necessary in most applications, a decoupling capaci tor of 0.1f or smaller may be connected between rdel and v ss . 8 uvlo undervoltage set point. a resistor can be connected between this pin and v ss to program the undervoltage set point - see figure 18. with this pin not connected, the under voltage disable is typically 6.6v. when this pin is tied to v dd , the under voltage disa ble is typically 6.2v. 9 rfsh refresh pulse setting. an external capacitor can be connected from this pin to v ss to increase the length of the start up refresh pulse - see figur e 16. if this pin is not connected, the refresh pulse is typically 1.5s. 10 dis disable input. logic level input that when taken high sets all six outputs low. dis high overrides all other inputs. with dis low, the ou tputs are controlled by the other inputs. dis can be driven by signal levels of 0v to 15v (no greater than v dd ).
hip4086, HIP4086A 4 fn4220.9 february 1, 2013 17 24 14 aho bho cho (xho) high-side outputs. connect to the gates of the high-side power mosfets in each phase. 20 v dd positive supply. decouple this pin to v ss (pin 6). 21 22 19 alo blo clo (xlo) low-side outputs. connect the gates of the low-side power mosfets to these pins. note: x = a, b or c. pin descriptions (continued) pin number symbol description ordering information part number (notes 1, 3) part marking temp range (c) charge pump package pkg. dwg. # HIP4086Ab HIP4086Ab -40 to +125 yes 24 ld soic m24.3 HIP4086Abz (note 2) HIP4086Abz -40 to +125 yes 24 ld soic (pb-free) m24.3 HIP4086Apz (note 2) HIP4086Apz -40 to +125 yes 24 ld pdip (pb-free) e24.3 HIP4086Aabz (note 2) HIP4086Aabz -40 to +125 no 24 ld soic (pb-free) m24.3 notes: 1. add ?-t*?, suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for hip4086, HIP4086A . for more information on msl, please see technical brief tb363 .
hip4086, HIP4086A 5 fn4220.9 february 1, 2013 absolute maximum ratings (note 7) thermal information supply voltage, v dd relative to gnd . . . . . . . . . . . . . . . . . . . . . -0.3v to 16v logic inputs (xli, xhi ) . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to v dd + 0.3v voltage on xhs . . . . . . . . . . . . . . -6v (transient) to 85v (-40 c to +150 c) voltage on xhb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v xhs - 0.3v to v xhs +v dd voltage on xlo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ss - 0.3v to v dd +0.3v voltage on xho . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v xhs - 0.3v to v xhb +0.3v phase slew rate (on xhs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20v/ns maximum recommended operating conditions supply voltage, v dd relative to gnd . . . . . . . . . . . . . . . . . . . . . . . 7v to 15v logic inputs (xli, xhi ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to vdd voltage on xhb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vxhs + vdd voltage on xhs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to 80v ambient temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c junction temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +150c thermal resistance (typical) ja (c/w) jc (c/w) soic package (notes 4, 6) . . . . . . . . . . . . . 75 22 soic package HIP4086Aabz (notes 5, 6) 51 22 pdip* package (notes 4, 6) . . . . . . . . . . . . 70 29 storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c operating junction temp range . . . . . . . . . . . . . . . . . . . .-40c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp *pb-free pdips can be used for through-hole wave solder processing only. they are not intended for use in refl ow solder processing applications. caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured with the component mounted on a low effective thermal conductivity test board in free air. see tech brief tb379 for details. 5. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 6. for jc , the ?case temp? location is taken at the package top center. 7. replace x with a, b, or c. dc electrical specifications v dd = v xhb = 12v, v ss = v xhs = 0v, r del = 20k, r uv = , gate capacitance (c gate ) = 1000pf, unless otherwise specified. boldface limits apply over the operating ju nction temperature ra nge, -40c to +150c. parameter test conditions t j = +25c t j = -40c to +150c units min (note 9) typ max (note 9) min (note 9) max (note 9) supply currents v dd quiescent current xhi = 5v, xli = 5v (hip4086) 2.7 3.4 4.2 2.1 4.3 ma xhi = 5v, xli = 5v (HIP4086A) 2.3 2.4 2.6 2.1 2.7 ma v dd operating current f = 20khz, 50% duty cycle (hip4086) 6.3 8.25 10.5 511 ma f = 20khz, 50% duty cycle (HIP4086A) 3.1 3.6 4.1 2.8 4.4 ma xhb on quiescent current xhi = 0v (hip4086) - 40 80 - 100 a xhi = 0v (HIP4086A) 80 100 200 a xhb off quiescent current xhi = v dd (hip4086) 0.6 0.8 1.3 0.5 1.4 ma xhi = v dd (HIP4086A) 0.8 0.9 1 0.7 1.2 ma xhb operating current f = 20khz, 50% duty cycle (hip4086) 0.7 0.9 1.3 - 2.0 ma f = 20khz, 50% duty cycle (HIP4086A) 0.8 0.9 1 - 1.2 ma xhb, xhs leakage current v xhs = 80v, v xhb = 93v 7 24 45 - 50 a charge pump, hip4086 only, (note 8) q pump output voltage no load 11.5 12.5 14 10.5 14.5 v q pump output current v xhs = 12v, v xhb = 22v 50 100 130 - 140 a undervoltage protection v dd rising undervoltage threshold r uv open 6.2 7.1 8.0 6.1 8.1 v v dd falling undervoltage threshold r uv open 5.75 6.6 7.5 5.6 7.6 v minimum undervoltage threshold r uv = v dd 5 6.2 6.8 4.9 6.9 v input pins: ali, bli, cli, ahi , bhi , chi , and dis low level input voltage - - 1.0 - 0.8 v
hip4086, HIP4086A 6 fn4220.9 february 1, 2013 high level input voltage 2.5 - - 2.7 -v input voltage hysteresis - 35 - - - mv low level input current v in = 0v -60 -100 -135 -55 -140 a high level input current v in = 5v -1 - +1 -10 +10 a gate driver output pins: alo, blo, clo, aho, bho, and cho low level output voltage (v out - v ss )i sinking = 30ma - 100 - - 200 mv peak turn-on current v out = 0v 0.3 0.5 0.7 - 1.0 a notes: 8. the specified charge pump current is the total amount available to drive external loads across xho and xhs. 9. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. ac electrical specifications v dd = v xhb = 12v, v ss = v xhs = 0v, c gate = 1000pf, r del = 10k, unless otherwise specified. boldface limits apply over the operating ju nction temperature rang e, -40c to +150c. parameter test conditions t j = +25c t j = -40c to +150c units min (note 9) typ max (note 9) min (note 9) max (note 9) turn-on delay and propagation delay dead time (figure 3) r del = 100k ? 3.8 4.5 6 37 s r del = 10k ? 0.38 0.5 0.65 0.3 0.7 s dead time channel matching r del = 10k ? -715 -20 % lower turn-off propagation delay (xli to xlo turn-off) (figure 3 or 4) no load - 30 45 -65 ns upper turn-off propagation delay (xhi to xho turn-off) (figure 3 or 4) no load - 75 90 -100 ns lower turn-on propagation delay (xli to xlo turn-on) (figure 3 or 4) no load - 45 75 -90 ns upper turn-on propagation delay (xhi to xho turn-on) (figure 3 or 4) no load - 65 90 -100 ns rise time c gate = 1000pf -2040 -50 ns fall time c gate = 1000pf -1020 -25 ns disable turn-off propagation delay (dis to xlo turn-off) (figure 5) -5580 -90 ns disable turn-off propagation delay (dis to xho turn-off) (figure 5) -8090 -100 ns disable to lower turn-on propagation delay (dis to xlo turn-on) (figure 5) -5580 -100 ns disable to upper enable (dis to xho turn-on) (figure 5) r del = 10k ? , c rfsh open -2.0- -- s dc electrical specifications v dd = v xhb = 12v, v ss = v xhs = 0v, r del = 20k, r uv = , gate capacitance (c gate ) = 1000pf, unless otherwise specified. boldface limits apply over the operating ju nction temperature ra nge, -40c to +150c. (continued) parameter test conditions t j = +25c t j = -40c to +150c units min (note 9) typ max (note 9) min (note 9) max (note 9)
hip4086, HIP4086A 7 fn4220.9 february 1, 2013 test waveforms and timing diagrams figure 3. prop delays with programmed turn-on de lays (rdel connected to vdd with a resistor) figure 4. prop delays with no programme d turn-on delays (rdel connected to vss) figure 5. disable function dead time xli to xlo turn-on + delay xli to xlo turn-off xli xlo xho xhi to xho turn-off dead time xhi xli to xlo turn-off xli to xho turn-off xhi to xho turn-on + delay xli to xlo turn-on xli to xlo turn-off xli xlo xho xhi xli to xlo turn-off xli to xlo turn-on xlo and xho are on simulateously xhi to xho turn-on xhi to xho turn-off xhi to xho turn-on dis or uv xlo xho xhi, xli dis to xlo turn-on delay xho turn-on delay refresh pulse dis to xho turn-off delay refresh pulse dis to xlo turn-on delay
hip4086, HIP4086A 8 fn4220.9 february 1, 2013 typical performance curves figure 6. v dd supply current vs v dd supply voltage figure 7. v dd supply current vs switching frequency figure 8. floating i xhb bias current figure 9. off-state i xhb bias current figure 10. charge pump output current (hip4086 only) figure 11. charge pump output voltage(hip4086 only)( -60 -40 -20 0 20 40 60 80 100 120 140 160 2 3 4 5 6 junction temperature (c) v dd supply current (ma) v dd = 7v v dd = 8v v dd = 10v v dd = 12v v dd = 15v v dd = 16v all gate control inputs = 5v -60 -40 -20 0 20 40 60 80 100 120 140 160 10 15 20 25 30 junction temperature (c) v dd supply current (ma) 200khz c gate = 1000pf 20khz 50khz 100khz 10khz 0 20 40 60 80 100 120 140 160 180 200 0 1000 2000 3000 4000 switching frequency (khz) floating bias current (a) c gate = no load c gate = 1000pf t j = +25c junction temperature (c) -60 -40 -20 0 20 40 60 80 100 120 140 160 0.6 0.8 1.0 1.2 1.4 1.6 1.8 bias current (ma) v dd = 10v v dd = 12v v dd = 15v v dd = 7v v dd = 8v -60 -40 -20 0 20 40 60 80 100 120 140 160 200 150 100 50 0 junction temperature (c) output current (a) v xhb - v xhs = 10v -60 -40 -20 0 20 40 60 80 100 120 140 160 6 7 8 9 10 11 12 13 14 junction temperature (c) charge pump output voltage (v) v dd = 7v v dd = 12v v dd = 10v v dd = 8v v dd = 15v
hip4086, HIP4086A 9 fn4220.9 february 1, 2013 figure 12. average turn-on current (0 to 5v) figure 13. average turn-off current (v dd to 4v) figure 14. rise and fall times (10 to 90%) figure 15. propagation delay figure 16. disable pin propagation delay figure 17. refresh time typical performance curves (continued) -60 -40 -20 0 20 40 60 80 100 120 140 160 0 0.2 0.4 0.6 0.8 1 junction temperature (c) average turn-on current (a) c gate = 1000pf v dd = 15v v dd = 8v v dd = 10v v dd = 12v v dd = 7v -60 -40 -20 0 20 40 60 80 100 120 140 160 0 0.4 0.8 1.2 1.6 2 junction temperature (c) average turn-off current (a) c gate = 1000pf v dd = 15v v dd = 8v v dd = 10v v dd = 12v v dd = 7v -60 -40 -20 0 20 40 60 80 100 120 140 160 0 10 20 30 40 junction temperature (c) rise and fall times (ns) rise fall v dd = xhb-xhs = 12v, c gate = 1000pf -60 -40 -20 0 20 40 60 80 100 120 140 160 20 40 60 80 100 junction temperature (c) propagation delay (ns) xhi to xho xli to xlo junction temperature (c) -60 -40 -20 0 20 40 60 80 100 120 140 160 10 100 propagation delay (ns) lower enable turn-on lower disable turn-off upper disable turn-off c rfsh (pf) 0 50 100 150 200 250 300 350 400 450 500 0 20 40 60 80 refresh time (s) t j = +25c
hip4086, HIP4086A 10 fn4220.9 february 1, 2013 functional description input logic note: when appropriate for brevity, input and output pins will be prefixed with an ?x? as a substitute for a, b, or c. for example, xhs refers to pins ahs, bhs, and chs. the hip4086/a is a three phas e bridge driver designed specifically for motor drive applications. three identical half bridge sections, a, b, and c, ca n be controlled individually by their input pins, ali, ahi , bli, bhi , and cli, chi (xli, xhi ) or the 2 corresponding input pins for each section can be tied together to form a pwm input (xli connected to xhi = xpwm). when controlling individual inputs, the programmable dead time is optional but shoot-thru protection must then be incorporated in the timing of the input signals. if the pwm mode is chosen, then the internal programmable dead time must be used. shoot-thru protection dead time, to prevent shoot-thru, is implemented by delaying the turn-on of the high-side and low-side drivers. the delay timers are enabled if the voltage on the rd el pin is greater than 100mv. the voltage on rdel will be grea ter than 100mv for any value of programming resistor in the specified range. if the voltage on rdel is less than 100mv, the de lay timers are disabled and no shoot-thru protection is provided by the internal logic of the hip4086/a. when the dead time is to be disabled, rdel should be shorted to vss. refresh pulse to insure that the boot capacitors are charged prior to turning on the high-side drivers, a refresh pu lse is triggered when dis is low or when the uv comparator transitions low (vdd is greater than the programmed undervoltage threshold). please refer to the ?block diagram (for clarity, only one phase is shown)? on page 2. when triggered, the refresh pulse turns on all of the low-side drivers (xlo = 1) and turns off all of the high-side drivers (xho = 0) for a duration set by a resistor tied between rdel and vss. when xlo = 1, the low-side bridge fets charge the boot caps from vdd through the boot diodes. figure 18. dead time figure 19. undervoltage threshold figure 20. i xhs leakage current typical performance curves (continued) junction temperature (c) -60 -40 -20 0 20 40 60 80 100 120 140 160 0 2 4 6 dead time (s) rdel = 100k ? rdel = 10k ? junction temperature (c) undervoltage shutdown/ -60 -40 -20 0 20 40 60 80 100 120 140 160 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 enable voltage enable (50k ? , uvlo to gnd) trip (50k, uvlo to gnd) enable (uvlo open) trip (uvlo open) trip/enable (0k ? , uvlo to v dd ) junction temperature (c) -60 -40 -20 0 20 40 60 80 100 120 140 160 10 15 20 25 leakage current (a) v xhs = 80v
hip4086, HIP4086A 11 fn4220.9 february 1, 2013 charge pump the internal charge pump of the hip4086/a is used to maintain the bias on the boot cap for 100% duty cycle. there is no limit for the duration of this period. the user must understand that this charge pump is only intended to provide the static bias current of the high-side drivers and the gate leakage current of the high-side bridge fets. it cannot provide in a reasonable time, the majority of the charge on the b oot cap that is consumed, when the xho drivers source the gate charge to turn on the high-side bridge fets. the boot caps should be sized so that they do not discharge excessively when sourcing the gate charge. see ?application information? on page 11 for methods to size the boot caps. the charge pump has sufficient capacity to source a worst-case minimum of 50a to the external load. the gate leakage current of most power mosfets is about 100na so there is more than sufficient current to maintain the charge on the boot caps. because the charge pump current is small, a gate-source resistor on the high-side bridge fets is not recommended. when calculating the leakage load on th e outputs of xhs, also include the leakage current of the boot capacitor. this is rarely a problem but it could be an issue with electrolytic capacitors at high temperatures. application information selecting the boot capacitor value the boot capacitor value is chosen not only to supply the internal bias current of the high-side driver but also, and more significantly, to provide the gate charge of the driven fet without causing the boot voltage to sag excessively. in practice, the boot capacitor should have a total charge that is about 20 times the gate charge of the driven power fet for approximately a 5% drop in voltage after charge has been transferred from the boot capacitor to the gate capacitance. the following parameters shown in table 1 are required to calculate the value of the boot capacitor for a specific amount of voltage droop when using the hi p4086/a (no charge pump). in table 1, the values used are arbitr ary. they should be changed to comply with the actual application. equation 1 calculates the total charge required for the period duration. this equation assumes that all of the parameters are constant during the period durati on. the error is insignificant if ripple is small. if the gate to source resistor is removed (r gs is usually not needed or recommended), then: c boot = 0.33f these values of c boot will sustain the high si de driver bias during period with only a small amount of ripple. but in the case of the hip4086, the charge pump reduces the value of c boot even more. the specified charge pump current is a minimum of 50a which is more than sufficient to source i gate_leak . also, because the specified charge pump current is in excess of what is needed for i hb , the total charge required to be sourced by the boot capacitor is just not only is the required boot cap smaller in value, there is no restriction on the duration of period. table 1. v dd = 10v v dd can be any value between 7 and 15vdc v hb = v dd - 0.6v = v ho high side driver bias voltage (v dd - boot diode voltage) referenced to v hs period = 1ms this is the longest expected switching period i hb = 100a worst case high side driver current when xho = high (this value is specified for v dd = 12v but the error is not significant) r gs = 100k gate-source resistor (usually not needed) ripple = 5% desired ripple voltage on the boot cap (larger ripple is not recommended) i gate_leak = 100na from the fet vendor?s datasheet qgate80v = 64nc from figure 21. q c q gate80v = period (i hb v ho r gs i gate_leak + ? ) ++ (eq. 1) c boot q c = ripple ? vdd () ? c boot 0.52 f = q c q gate80v = orc boot 0.13 f = (eq. 2) figure 21. typical gate voltage vs gate charge
hip4086, HIP4086A 12 fn4220.9 february 1, 2013 typical application circuit figure 22 is an example of how the hip4086 and HIP4086A 3-phase drivers can be applied to drive a 3-phase motor. depending on the application, th e switching speed of the bridge fets can be reduced by adding series connected resistors between the xho outputs and the fet gates. gate-source resistors are recommended on the low-side fets to prevent unexpected turn-on of the bridge should the bridge voltage be applied before v dd . gate-source resistors on the high-side fets are not usually required if low- side gate-source resistors are used. if relatively small gate-s ource resistors are used on the high-side fets, be aware that they will load the charge pump of the hip4086 negating the ability of the charge pump to keep the high-side driver biased during very long periods. an important operating condition that is frequently overlooked by designers is the negative transient on the xhs pins that occurs when the high-side bridge fet turns off. the absolute maximum transient allowed on the xhs pin is -6v but it is wise to minimize the amplitude to lower levels. this transient is the result of the parasitic inductance of the low-side drain-source conductor on the pcb. even the parasitic inductance of the low-side fet contributes to this transient. when the high-side bridge fet turn s off, because of the inductive characteristics of a motor load, the current that was flowing in the high-side fet (blue) must rapidly commutate to flow through the low-side fet (red). the amplitude of the negative transient impressed on the xhs node is (d i/dt x l) where l is the total parasitic inductance of the low-side fet drain-source path and di/ddt is the rate at which the hi gh-side fet is turned off. with the increasing power levels of new generation motor drives, clamping this transient becomes more and more significant for the proper operation of the hip4086/a. there are several ways of reducing the amplitude of this transient. if the bridge fets are turned off more slowly to reduce di/dt, the amplitude will be redu ced but at the expense of more switching losses in the fets. carefu l pcb design will also reduce the value of the parasitic inductance. however, these two solutions by themselves may not be sufficient. figure 23 illustrates a simple me thod for clamping the negative transient. two series connected, fast pn junction, 1a diodes are connected between xhs and vss as shown. it is important that the components be placed as close as possible to the xhs and vss pins to minimize the parasitic inductance of this current path. two series connected diodes are required because they are in parallel with the body diode of th e low-side fet. if only one diode is used for the clamp, it will co nduct some of the negative load current that is flowing in the low-side fet. in severe cases, a small value resistor in series with the xhs pin as shown, will further reduce the amplitude of the negative transient. please note that a similar transien t with a positive polarity occurs when the low-side fet turns off. this is less frequently a problem because xhs node is floating up toward the bridge bias voltage. the absolute max voltage rating for the xhs node does need to be observed when the positive transient occurs. controller aho clo blo alo cho bho cli bli ali chi bhi ahi chs ahs bhs chb ahb bhb vdd rdel vdd speed brake battery 24v...48v hip4086/a vss figure 22. typical application circuit figure 23. bridge with parasitic inductances vss xhs xlo xho inductive load + - + -
hip4086, HIP4086A 13 fn4220.9 february 1, 2013 general pcb layout guidelines the ac performance of the hip4086/a depends significantly on the design of the pc board. the following layout design guidelines are recommended to achieve optimum performance: ? place the driver as close as possible to the driven power fets. ? understand where the switching power currents flow. the high amplitude di/dt currents of the driven power fet will induce significant voltage transients on the associated traces. ? keep power loops as short as possible by paralleling the source and return traces. ? use planes where practical; they are usually more effective than parallel traces. ? avoid paralleling high amplitud e di/dt traces with low level signal lines. high di/dt will induce currents and consequently, noise voltages in the low level signal lines. ? when practical, minimize impedances in low level signal circuits. the noise, magnetically induced on a 10k ? resistor, is 10x larger than the noise on a 1k ? resistor. ? be aware of magnetic fields emanating from motors, transformers and inductors. gaps in these magnetic structures are especially bad for emitting flux. ? if you must have traces close to magnetic devices, align the traces so that they are parallel to the flux lines to minimize coupling. ? the use of low inductance comp onents such as chip resistors and chip capacitors is highly recommended. ? use decoupling capacitors to reduce the influence of parasitic inductance in the vdd and gnd leads. to be effective, these caps must also have the shortest possible conduction paths. if vias are used, connect several paralleled vias to reduce the inductance of the vias. ? it may be necessary to add resi stance to dampen resonating parasitic circuits especially on xho and xlo. if an external gate resistor is unacceptable, then th e layout must be improved to minimize lead inductance. ? keep high dv/dt nodes away from low level circuits. guard banding can be used to shunt away dv/dt injected currents from sensitive circuits. this is especially true for control circuits that source the input signals to the hip4086/a. ? avoid having a signal ground plane under a high amplitude dv/dt circuit. this will inject di/dt currents into the signal ground paths. ? do power dissipation and voltage drop calculations of the power traces. many pcb/cad programs have built in tools for calculation of trace resistance. ? large power components (power fets, electrolytic caps, power resistors, etc.) will have internal parasitic inductance which cannot be eliminated. this must be accounted for in the pcb layout and circuit design. ? if you simulate your circuits, consider including parasitic components especially parasitic lead inductance.
hip4086, HIP4086A 14 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn4220.9 february 1, 2013 for additional products, see www.intersil.com/product_tree about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the fastest growing markets wi thin the industrial and infrastructure, personal computing and high-end consumer markets. for more inform ation about intersil or to find out how to become a member of our winning team, visit our website and career page at www.intersil.com . for a complete listing of applications, re lated documentation and related parts, plea se see the respective product information page. also, please check the product information page to ensure that you have the most updated datasheet: hip4086, HIP4086A to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff reliability reports are available from our website at: http://rel.intersil.com/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change january 28, 2013 fn4220.9 corrected following typo in the second paragraph of page 1: from: (0.5ms to 4.5ms) to: (0.5s to 4.5s) september 27, 2012 fn4220.8 removed evaluation board from ?ordering information? and ?rel ated literature? since it is inactive. june 1, 2011 fn4220.7 added alternate parameters for HIP4086A in dc electrical specifications table supply currents on page 5. added to charge pump figures 10 and 11 in typical performance curves "hip4086 only" march 18, 2011 -converted to new intersil datasheet template. -changed title from "80v, 500ma, 3-phase driv er" to "80v, 500ma, 3-phase mosfet driver". -rewrote description on page 1 by adding HIP4086A and stating the differences between parts. -updated ?ordering information? on page 4 by adding part number HIP4086Aabz an d eval board. added msl note. removed obsolete part HIP4086Ap. -updated ?typical application? on page 1. -added ?charge pump output current? on page 1. -updated ?features? and ?applications? section on page 1. -added ?related literature? on page 1. -updated ?block diagram? on page 2 by adding color and notes. -updated ?thermal information? and notes on page 5. -added ?boldface limits apply..? to common conditions of electrical specifications tables. added note 9 to min and max columns of electrical specifications tables. -updated all timing diagrams for better clarification on page 7. -added ?functional description?, ?application informatio n? and ?general pcb layout guidelines? sections beginning on page 10. -updated package outline drawing m24.3 by removing table listing dimensions and putting dimensions on drawing. added land pattern. -added ?revision history? and ?about intersil? to page 14. july 26, 2004 fn4220.6 added pb-free parts to ?ordering information? on page 4. february 18, 2003 fn4220.5 revised ?pin descriptions? on page 3. revised ?low level input current? specs on page 6. may, 1999 fn4220.4 initial release.
hip4086, HIP4086A 15 fn4220.9 february 1, 2013 dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in ca se of conflict between english and metric dimensions, the in ch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are m easured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not in clude dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e24.3 (jedec ms-001-af issue d) 24 lead narrow body dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8 c 0.008 0.014 0.204 0.355 - d 1.230 1.280 31.24 32.51 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n24 249 rev. 0 12/93
hip4086, HIP4086A 16 fn4220.9 february 1, 2013 package outline drawing m24.3 24 lead wide body small outline plastic package (soic) rev 2, 3/11 top view notes: 1. dimensioning and tolerancing per ansi y14.5m-1982. 2. package length does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. package width does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 5. terminal numbers are shown for reference only. 6. the lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. controlling dimension: millimeter. converted inch dimensions in ( ) are not necessarily exact. 8. this outline conforms to jedec publication ms-013-ad issue c. side view ?a? side view ?b? typical recommended land pattern index area 24 123 seating plane detail "a" x 45 7.60 (0.299) 7.40 (0.291) 0.75 (0.029) 0.25 (0.010) 10.65 (0.419) 10.00 (0.394) 1.27 (0.050) 0.40 (0.016) 15.60 (0.614) 15.20 (0.598) 2.65 (0.104) 2.35 (0.093) 0.30 (0.012) 0.10 (0.004) 1.27 (0.050) 0.51 (0.020) 0.33 (0.013) 0.32 (0.012) 0.23 (0.009) 8 0 1.981 (0.078) 9.373 (0.369) 0.533 (0.021) 1.27 (0.050)

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